1. Field of the Invention
The present invention relates generally to digital phase locked loop circuits and more particularly, is directed to a digital phase locked loop circuit for use in a demodulating circuit which demodulates data reproduced from a floppy disk or the like.
2. Description of the Prior Art
When data shown in FIG. 1A is written on a floppy disk according to the recording system with double density recording, data is modified-frequency-modulated (MFM) as shown in FIG. 1B and then recorded on the flopy disk. T assumes a time between data bits. Then, the pulse interval of the MFM-modulated data is represented as one of 2T, 3T or 4T.
When data is read out of the floppy disk, a window signal indicating the section between the adjacent bits as shown in FIG. 1C is formed from the MFM-modulated pulse by which the MFM-modulated data is demodulated to produce reproduced data shown in FIG. 1D.
The circuit for generating the window signal is called a data separator circuit or variable frequency oscillator (VFO) circuit. In most cases of the MFM recording, the window signal generating circuit is formed of an analog phase locked loop circuit.
Though fabricated as an integrated circuit (IC), the analog phase locked loop circuit (hereinafter simply referred to as a PLL circuit) has to connect a resistor and a capacitor to the outside of the integrated circuit. This increases the number of external connection pins for the integrated circuit inevitably. Further, the analog PLL circuit needs a proper adjustment and its temperature characteristic is not satisfactory.
To remove the above-mentioned defects, there is a known digital PL circuit shown in FIG. 2. This conventional digital PLL circuit will be described hereinafter with reference to FIG. 2.
As FIG. 2 shows, there is shown a PLL circuit 10 which comprises a digital phase comparator circuit 11, a digital low-pass filter 12 and a counter 13. The counter 13 frequency-divides a clock CK supplied thereto from a clock generator circuit or crystal oscillator (not shown) and changes its frequency-divided value so as to function as a voltage controlled oscillator (VCO). The repetitive cycle of the clock CK is selected as, by way of example, T/16.
Data reproduced from the floppy disk, however, contains a jitter component caused by the irregular revolution of a drive motor, an extraneous noise component or the like so that when data bit and clock bit are separated from, for example, MFM-modulated data, quantization error or sampling error of the digital PLL circuit raises a serious problem.
When an incoming data having a pulse interval, 4.05T (.apprxeq.65 clock cycles) shown in FIG. 3A is supplied to the conventional digital PLL circuit 10 shown in FIG. 2, the output from the digital low-pass filter 12 changes from [0] to [1] as shown in FIG. 3B so that as shown in FIG. 3C, the count value (frequency-dividing ratio) of the counter 13 changes from [16] to [17]. Thus, the pulse interval, 4.05T of the input data is regarded as 17.times.4=68 clock cycles.
In this state, the pulse interval of the input data becomes shorter than 4 cycles of the output from the counter 13 and thus the output from the digital phase comparator circuit 11 tends to become negative. However, the digital low-pass filter 12 is arranged so as not to follow the afore-mentioned rapid change so that after a predetermined period in which the counter 13 holds its count value, [17], the counter 13 changes its count value from [17] to [16]. If the counter 13 holds this count value, i.e., [16] during a predetermined period, the 4 periods of the output from the counter 13 is presented as 16.times.4=64 clock cycles which are shorter than the practical pulse interval of the input data, i.e, 65 clock cycles. Thus, the output from the digital phase comparator circuit 11 is gradually returned to be positive and then inverted to be positive at a certain time point. After the lapse of the predetermined time period, the output from the digital low-pass filter 12 changes from [0] to [1] so that the counter 13 produces the count value, [17] again.
Since the conventional digital PLL circuit cannot avoid the sampling error as described above, a follow-up characteristic for input data of the digital PLL circuit is inferior as compared with that of the analog PLL circuit.
In general, data reproduced from the floppy disk contains a frequency fluctuation component of relatively low frequency caused by the irregular revolution of the drive motor and so on. Also, when data written in the floppy disk has a particular bit pattern, mutual interference of data pulse causes the position of pulse to be shifted, thus producing a frequency fluctuation component of high frequency which might be called a peak shift.
Therefore, the digital PLL circuit has to follow the low frequency fluctuation component satisfactorily and must not follow the so-called peak shift so as to read the data erroneously. In order to realize the afore-mentioned characteristics, the cutoff frequency of the digital low-pass filter 12 is selected, for example, to be 10 kHz.
Accordingly, when incoming data having frequency fluctuation component sufficiently higher than the cutoff frequency of the digital low-pass filter 12, i.e., peak-shifted data is applied to an input terminal IN of the PLL circuit 10 shown in FIG. 2, the output from the phase comparator circuit 11 changes in response to this quick fluctuation while the output from the digital low-pass filter 12 should become [0] inherently. However, due to the measuring error of the digital low-pass filter 12, the above output does not become [0] and there may appear an output signal.
When input .circle.A data having high frequency fluctuation component due to the peak shift phenomenon as, for example, shown in FIG. 4A is supplied to the input terminal IN of the PLL circuit 10, the output, which changes as [0], [-5], [0] and [+5], from the digital phase comparator circuit 11 is supplied to the digital low-pass filter 12. As mentioned before, the digital low-pass filter 12 is not responsive to the high frequency so that the output thereof should become [0]. However, due to the measuring error thereof, at time point in which the phase error, [+5] is inputted to the digital low-pass filter 12, [+1] appears as the output of the digital low-pass filter 12 as shown in FIG. 4D. As a result, as shown in FIG. 4E, the frequency-divided value of the counter 13 changes from [16] to [17] and hence the digital PLL circuit 10 follows the peak shift. Thus, as shown in FIG. 4C, the phase error remains in several input data.
Because of the above-mentioned measuring error, as compared with the analog PLL circuit, the conventional digital PLL circuit is not stable for input data containing peak shift component.